View CS5381_2379351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) cirrus logic, inc. http://www.cirrus.com CS5381 120 db, 192 khz, multi-bit audio a/d converter features advanced multi-bit delta-sigma architecture 24-bit conversion 120 db dynamic range -110 db thd+n supports all audio sample rates including 192 khz less than 260 mw power consumption high pass filter or dc offset calibration supports logic levels between 5 and 2.5 v differential analog architecture low latency digital filtering overflow detection pin compatible with the cs5361 general description the CS5381 is a complete analog-to-digital converter for digital audio systems. it performs sampling, analog-to- digital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 khz per channel. the CS5381 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. the adc uses a differential architecture which provides excellent noise rejection. the CS5381 is ideal for audi o systems requiring wide dy- namic range, negligible distortion and low noise, such as a/v receivers, dvd-r, cd-r, digital mixing consoles, and effects processors. ordering information CS5381-ks -10 to 70 c 24-pin soic CS5381-kz -10 to 70 c 24-pin tssop CS5381-kzz -10 to 70 c 24-pin tssop cdb5381 evaluation board voltage reference serial output interface digital filter high pass filter high pass filter decimation digital filter decimation dac - + s/h dac - + s/h ainr+ sclk sdout mclk rst vq lrck ainr- ainl+ ainl- filt+ i 2 s/lj m/s hpf mode0 mode1 refgnd v l mdiv lp filter lp filter ? ? ovfl gnd va 5.0 v gnd vd 3.3v - 5.0v 2.5 v - 5.0 v aug ?04 ds563a4
CS5381 2 table of contents 1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 characteristics and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 specified operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog characteristics (CS5381-ks/kz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 switching characteristics - serial audio port . . . . . . . . . . . . . . . . . . . . . . . . . 10 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 typical connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 operational mode/sample rate range select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 system clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.4 analog connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.5 high pass filter and dc offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 overflow detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6.1 ovfl output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 grounding and power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 synchronization of multiple devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 capacitor size on the reference pin (filt+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm important notice ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant infor mation to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patent s or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any p atents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information con tained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (critical applications). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life support products or other critical applications (including medical devices, aircraft systems or components and personal or automotive safety or security devices). inclusion of cirrus products in such applications is understood to be fully at the custom- ers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trade- marks or service marks of their respective owners.
CS5381 3 list of figures figure 1. single speed mode stopband rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. single speed mode transition band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. single speed mode transition band (detail). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. single speed mode passband ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. double speed mode stopband rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. double speed mode transition band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. double speed mode transition band (detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. double speed mode passband ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. quad speed mode stopband rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10. quad speed mode transition band. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 11. quad speed mode transition band (detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 12. quad speed mode passband ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 13. master mode, left justified sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 14. slave mode, left justified sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 15. master mode, i 2 s sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 16. slave mode, i 2 s sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 17. ovfl output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 18. left justified serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 19. i 2 s serial audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 20. ovfl output timing, i2s format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 21. ovfl output timing, left-justified format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 22. typical connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. CS5381 master mode clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. recommended analog input buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 25. cs 5381 thd + n versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 list of tables table 1. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2. CS5381 mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 3. CS5381 common master clock frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. CS5381 slave mode clock ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 1. revision history release date changes a1 december, 2002 initial release a2 october, 2003 changed front page description of digital filter (page 1) improved distortion specification from -105 db to -110 db (page 6) modified serial port timing specifications for slave mode operation (page 8) added pull-down resistors to recommended input buffer (page 15) a3 may, 2004 changed full-scale voltage specification to reflect va supply voltage (page 6) added applications section about capacitor value on filt+ pin (page 19) changed input impedance specification from 37 to 2.5 k ? (page 6) changed impedance specification on filt+ from 35 to 4.5 k ? (page 13) a4 august, 2004 add lead free part number.
CS5381 4 1 pin descriptions power supply and ground pin name # pin description rst 1 reset ( input ) - the device enters a low power mode when low. m/s 2 master/slave mode (input) - selects operation as either clock master or slave. lrck 3 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. mclk 5 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 6 digital power ( input ) - positive power supply for the digital section. gnd 7,18 ground ( input ) - ground reference. must be connected to analog ground. vl 8 logic power ( input ) - positive power for the digital input/output. sdout 9 serial audio data output ( output ) - output for two?s complement serial audio data. mdiv 10 mclk divider (input ) - enables a master clock divide by two function. hpf 11 high pass filter enable (input ) - enables the digital high-pass filter. i 2 s/lj 12 serial audio interface format select ( input ) -selects either the left-justified or i 2 s format for the sai. m0 m1 13, 14 mode selection ( input ) - determines the operational mode of the device. ovfl 15 overflow (output, open drain) - detects an overflow condition on both left and right channels. ainl+ ainl- 16, 17 differential left channel analog input ( input ) - signals are presented differentially to the delta-sigma modulators via the ainl+/- pins. va 19 analog power ( input ) - positive power supply for the analog section. ainr- ainr+ 20, 21 differential right channel analog input ( input ) -signals are presented differentially to the delta-sigma modulators via the ainr+/- pins. vq 22 quiescent voltage (output) - filter connection for the internal quiescent reference voltage. ref_gnd 23 reference ground ( input ) - ground reference for the internal sampling circuits. filt+ 24 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. rst 124 filt+ m/s 223 refgnd lrck 322 vq sclk 421 ainr + mclk 520 ainr - vd 619 va gnd 718 gnd vl 817 ainl- sdout 916 ainl+ mdiv 10 15 ovfl hpf 11 14 m1 i 2 s/lj 12 13 m0
CS5381 5 2 characteristics and specifications all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical per- formance characteristics and specifications are derived from measurements taken at va = 5.0 v, vd = vl = 3.3 v, and ta = 25 c. specified operating conditions (gnd = 0 v; all voltages with respect to 0 v.) absolute maximum ratings (gnd = 0 v, all voltages with respect to ground.) (note 3) notes: 1. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause src latch-up. 2. the maximum over/under voltage is limited by the input current. 3. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply dc power supplies: positive analog positive digital positive logic va vd vl 4.75 3.1 2.37 5.0 - - 5.25 5.25 5.25 v v v ambient operating temperature (power applied) t a -10 - +70 c parameter symbol min typ max units dc power supplies: analog logic digital va vl vd -0.3 -0.3 -0.3 - - - +6.0 +6.0 +6.0 v v v input current (note 1) i in -- 10 ma analog input voltage (note 2) v in gnd-0.7 - va+0.7 v digital input voltage (note 2) v ind -0.7 - vl+0.7 v ambient operating temperature (power applied) t a -50 - +95 c storage temperature t stg -65 - +150 c
CS5381 6 analog characteristics (CS5381-ks/kz) test conditions (unless otherwise speci- fied): input test signal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. notes: 4. referred to the typical full-scale input voltage. 5. measured between ain+ and ain-. parameter symbol min typ max unit single speed mode fs = 48 khz dynamic range a-weighted unweighted 114 111 120 117 - - db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db thd+n - - - -110 -97 -57 -104 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 114 111 - 120 117 114 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -110 -97 -57 -107 -104 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 114 111 - 120 117 114 - - - db db db total harmonic distortion + noise (note 4) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -110 -97 -57 -107 -104 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5% gain drift - 100 - ppm/c offset error hpf enabled hpf disabled - - 0 100 - - lsb lsb analog input characteristics full-scale input voltage 1.07*va 1.13*va 1.18*va vpp input impedance (differential) (note 5) - 2.5 - k ? common mode rejection ratio cmrr - 100 - db
CS5381 7 digital filter characteristics notes: 6. the filter frequency response scales precisely with fs. 7. response shown is for fs equal to 48 khz. filter characteristics scale with fs. parameter symbol min typ max unit single speed mode (2 khz to 50 khz sample rates) passband (-0.1 db) (note 6) 0 - 0.47 fs passband ripple - - 0.035 db stopband (note 6) 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs - s double speed mode (50 khz to 100 khz sample rates) passband (-0.1 db) (note 6) 0 - 0.45 fs passband ripple - - 0.035 db stopband (note 6) 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs - s quad speed mode (100 khz to 200 khz sample rates) passband (-0.1 db) (note 6) 0 - 0.24 fs passband ripple - - 0.035 db stopband (note 6) 0.78 - - fs stopband attenuation -97 - - db total group delay (fs = output sample rate) t gd -5/fs - s high pass filter characteristics frequency response -3.0 db -0.13 db (note 7) -1 20 - - hz hz phase deviation @ 20 hz (note 7) - 10 - deg passband ripple - - 0 db filter setting time 10 5 /fs s
CS5381 8 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 1. single speed mode stopband rejection figure 2. single speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 3. single speed mode transition band (detail) figure 4. single speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 5. double speed mode stopband rejection figure 6. double speed mode transition band
CS5381 9 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 7. double speed mode transition band (detail) figure 8. double speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 9. quad speed mode stopband rejection figure 10. quad speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 11. quad speed mode transition band (detail) figure 12. quad speed mode passband ripple
CS5381 10 switching characteristics - serial audio port (logic ?0? = gnd = 0 v; logic ?1? = vl, c l = 20 pf) parameter symbol min typ max unit output sample rate single speed mode double speed mode quad speed mode fs fs fs 2 50 100 - - - 54 108 200 khz khz khz ovfl to lrck edge setup time t setup 16/f sclk --s ovfl to lrck edge hold time t hold 1/f sclk --s ovfl time-out on overrange condition fs = 44.1, 88.2, 176.4 khz fs = 48, 96, 192 khz - - 740 680 - - ms ms mclk specifications mclk period t clkw 36 - 1953 ns mclk duty cycle t clkhl 40 - 60 % master mode sclk falling to lrck t mslr -20 - 20 ns sclk falling to sdout valid t sdo 0 - 32 ns sclk duty cycle - 50 - % slave mode single speed output sample rate fs 2 - 54 khz lrck duty cycle 405060% sclk period t sclkw 163 - - ns sclk low t sclkhl 55 - - ns sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -20 - 20 ns double speed output sample rate fs 50 - 108 khz lrck duty cycle 405060% sclk period t sclkw 163 - - ns sclk low t sclkhl 55 - - ns sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -20 - 20 ns quad speed output sample rate fs 100 - 200 khz lrck duty cycle 405060% sclk period t sclkw 81 - - ns sclk low t sclkhl 40 - - ns sclk falling to sdout valid t dss - - 32 ns sclk falling to lrck edge t slrd -8 - 8 ns
CS5381 11 sclk output t mslr sdout t sdo lrck output msb msb-1 sclk input lrck input sclkl t dss t msb msb-1 msb-2 lrdss t sclkh t t sclkw sdout srd l t figure 13. master mode, left justified sai figure 14. slave mode, left justified sai sclk output t mslr t sdo lrck output msb sdout sclk input lrck input sclkl t dss t msb msb-1 sclkh t t sclkw sdout figure 15. master mode, i 2 s sai figure 16. slave mode, i 2 s sai ovfl t setup lrck t hold figure 17. ovfl output timing
CS5381 12 sdata 23 22 7 6 23 22 sclk lrck 23 22 54 32 10 8 76 54 32 10 8 9 9 left channel right channel figure 18. left justified serial audio interface sdata 23 22 8 7 23 22 sclk lrck 23 22 65 43 21 0 87 65 43 21 0 9 9 left channel right channel figure 19. i 2 s serial audio interface lrck ovfl sclk ovfl _r ovfl_ l ovfl _r figure 20. ovfl output timing, i 2 s format lrck ovfl sclk ovfl_ r ovfl _l ovfl _r figure 21. ovfl output timing, left-justified format
CS5381 13 dc electrical characteristics (gnd = 0 v, all voltages with respect to ground. mclk=12.288 mhz; master mode) notes: 8. power-down mode is defined as rst = low with all clocks and data lines held static. 9. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. digital characteristics parameter symbol min typ max unit power supply current va = 5 v (normal operation) vl,vd = 5 v vl,vd = 3.3 v i a i d i d - - - 36 36 24 40 40 27 ma ma ma power supply current va = 5 v (power-down mode) (note 8) vl,vd = 5 v i a i d - - 100 100 - - ua ua power consumption (normal operation) va, vl, vd = 5 v va = 5 v; vl, vd = 3.3 v (power-down mode) - - - - - - 360 259 1 400 289 - mw mw mw power supply rejection ratio (1 khz) (note 9) psrr - 65 - db v q nominal voltage output impedance maximum allowable dc current source/sink - - - 2.5 25 0.01 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - 5 4.5 0.01 - - - v k ? ma parameter symbol min typ max units high-level input voltage (% of vl) v ih 70% - - v low-level input voltage (% of vl) v il --30%v high-level output voltage at i o = 100 a (% of vl) v oh 70% - - v low-level output voltage at i o = 100 a (% of vl) v ol --15%v input leakage current i in -- 10 a
CS5381 14 3 typical connection diagram filt+ ainl+ ainl- v d 0.01 f a/d converter sclk CS5381 m/s mclk ainr+ ainr- vq **47 f + rst va v l +5v 1 f +5 vto 2.5 v 5.1 ? 1 f + + + sdout gnd i 2 s/lj lrck gnd power down and mode settings audio data processor timing logic and clock 0.01 f 0.01 f 0.01 f hpf m0 m1 refgnd mdiv +5 v to 3.3 v 1 f 0.01 f 1 f + analog input buffer (figure 24) analog input buffer (figure 24) ovfl 10 k vl * 0.01 f ** capacitor value affects low frequency distortion. see section 4.9. * resistor may only be used if vd is derived from va. if used, do not drive any other logic from vd. figure 22. typical connection diagram
CS5381 15 4 applications 4.1 operational mode/sample rate range select the output sample rate, fs, can be adjusted from 2 khz to 200 khz. the CS5381 must be set to the prop- er speed mode via the mode pins, m1 and m0. refer to table 2. 4.2 system clocking the device supports operation in either master mode, where the left/right and serial clocks are synchro- nously generated on-chip, or slave mode, which requires external generation of the left/right and serial clocks. the device also includes a master clock divider in master mode where the master clock will be internally divided prior to any other internal circuitry when mdiv is enabled, set to logic 1. in slave mode, the mdiv pin needs to be disabled, set to logic 0. 4.2.1 master mode in master mode, lrck and sclk operate as outputs. the left/right and serial clocks are internally derived from the master clock with the left/right clock equal to fs and the serial clock equal to 64x fs, as shown in figure 23. refer to table 3 for common master clock frequencies. m1 (pin 14) m0 (pin 13) mode output sample rate (fs) 0 0 single speed mode 2 khz - 54 khz 0 1 double speed mode 50 khz - 108 khz 1 0 quad speed mode 100 khz - 200 khz 11reserved table 2. CS5381 mode control 128 256 64 m0 m1 lrck output (equal to fs) single speed quad speed double speed 00 01 10 2 4 1 sclk output single speed quad speed double speed 00 01 10 2 1 0 1 mclk mdiv figure 23. CS5381 master mode clocking
CS5381 16 4.2.2 slave mode lrck and sclk operate as inputs in slave mode. it is recommended that the left/right clock be synchro- nously derived from the master clock and must be equal to fs. it is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x fs to maximize system performance. refer to table 4 for required clock ratios. * only available in master mode. table 4. CS5381 slave mode clock ratios 4.3 power-up sequence reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. it is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. the internal reference voltage must be stable for the device to produce valid data. therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of filt+ and the presence of the external capacitance. 4.4 analog connections the analog modulator samples the input at 6.144 mhz. the digital filter will reject signals within the stop- band of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to figure 24, which shows the suggested filter that will at- tenuate any noise energy at 6.144 mhz in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ce- ramics) must be avoided since these can degrade signal linearity. c0g capacitors are recommended for this application. single speed mode fs = 2 khz to 54 khz double speed mode fs = 50 khz to 108 khz quad speed mode fs = 100 khz to 200 khz mclk/lrck ratio 256x, 512x 128x, 256x 64x*, 128x sclk/lrck ratio 64x, 128x 64x 64x sample rate (khz) mdiv = 0 mclk (mhz) mdiv = 1 mclk (mhz) 32 8.192 16.384 44.1 11.2896 22.5792 48 12.288 24.576 64 8.192 16.384 88.2 11.2896 22.5792 96 12.288 24.576 176.4 11.2896 22.5792 192 12.288 24.576 table 3. CS5381 common master clock frequencies
CS5381 17 4.5 high pass filter and dc offset calibration the operational amplifiers in the input circuitry driving the CS5381 may generate a small dc offset into the a/d converter. the CS5381 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding ?clicks? when switching between devices in a multichannel system. the high pass filter continuously subtracts a measure of the dc offset from the output of the decimation filter. if the hpf pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1) running the CS5381 with the high pass filter enabled until the filter settles. see the digital filter char- acteristics for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. a system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5381. vq + 634 ? 634 ? 91 ? 91 ? + - - 2700 pf 470 pf 470 pf cog cog 10 uf 10 uf adc ain+ adc ain- ain+ ain- cog 100k ? 10 k ? 10 k ? 100k ? figure 24. recommended analog input buffer
CS5381 18 4.6 overflow detection the CS5381 includes overflow detection on both the left and right channels. this time multiplexed infor- mation is presented as open drain, active low on pin 15, ovfl . the ovfl_l and ovfl_r data will go to a logical low as soon as an overrange condition in either channel is detected. the data will remain low as specified in the switching characteristics - serial audio port section. this ensures sufficient time to detect an overrange condition regardless of the speed mode. after the timeout, the ovfl_l and ovfl_r data will return to a logical high if there has not been any other overrange condition detected. please note that an overrange condition on either channel will restart the timeout period for both channels. 4.6.1 ovfl output timing in left-justified format, the ovfl pin is updated one sclk period after an lrck transition. in i 2 s format, the ovfl pin is updated two sclk periods after an lrck transition. refer to figures 20 and 21. in both cases the ovfl data can be easily demultiplexed by using the lrck to latch the data. in left-justified for- mat, the rising edge of lrck would latch the right channel overflow status, and the falling edge of lrck would latch the left channel overflow status. in i 2 s format, the falling edge of lrck would latch the right channel overflow status and the rising edge of lrck would latch the left channel overflow status. 4.7 grounding and power supply decoupling as with any high resolution converter, the CS5381 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 22 shows the recommended power arrangements, with va and vl connected to clean supplies. vd, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. in this case, no additional devices should be powered from vd. decoupling capacitors should be as near to the adc as possible, with the low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.01 f, must be positioned to minimize the electri- cal path from filt+ and refgnd. the cdb5381 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the adc digital outputs only to cmos in- puts. 4.8 synchronization of multiple devices in systems where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the same for all of the CS5381?s in the sys- tem. if only one master clock source is needed, one solution is to place one CS5381 in master mode, and slave all of the other CS5381?s to the one master. if multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5381 reset with the falling edge of mclk. this will ensure that all converters begin sampling on the same clock edge.
CS5381 19 220 uf 100 uf 47 uf 22 uf 10 uf 1 uf 4.9 capacitor size on the reference pin (filt+) the CS5381 requires an external capacitance on the internal reference voltage pin, filt+. the size of this decoupling capacitor will affect the low frequency distortion performance as shown in figure 22, with larger capacitor values used to optimize low frequency distortion performance. figure 25. cs 5381 thd + n versus frequency
CS5381 20 5 package dimensions inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.598 0.614 15.20 15.60 e 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 24l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
CS5381 21 notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.303 0.307 0.311 7.70 7.80 7.90 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
CS5381 22 6 thermal characteristics 7 parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale analog input for a full-scale digital output. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv. parameter symbol min typ max unit allowable junction temperature - - 135 c junction to ambient thermal impedance ja -70 - c/w

▲Up To Search▲

Price & Availability of CS5381

	To Download CS5381 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .